Reading data from a row of memory cells in an integrated circuit memory device (e.g., DRAM) typically involves the selection of a row of memory cells connected to a word line in response to a row address and the transfer of data from the selected row of memory cells to a plurality of pairs of precharged and equalized differential bit lines BL and /BL. Sense amplifiers may also be used to sense the potentials of the bit lines and drive the differential bit lines BL and /BL to opposite logic potentials (e.g., logic 0 and logic 1) which represent the value of the data in a respective memory cell. Column address signals can then be used to sequentially transfer data from each of the pairs of differential bit lines BL and /BL to a pair of differential input/output lines IO and /IO, for example. These conventional operations of integrated circuit memory devices are more fully described in U.S. Pat. No. 5,701,268 to Lee et al. entitled "Sense Amplifier for Integrated Circuit Memory Devices Having Boosted Sense and Current Drive Capability and Methods of Operating Same"; U.S. Pat. No. 5,748,529 to Lee entitled "Integrated Circuit Memory Devices Having Direct Read Capability"; and U.S. Pat. No. 5,761,132 to Kim entitled "Integrated Circuit Memory Devices With Latch-Free Page Buffers Therein for Preventing Read Failures", assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference. Other conventional operations for operating integrated circuit memory devices are described in U.S. Pat. No. 5,640,030 to Kenney entitled "Double Dense Ferroelectric Capacitor Cell Memory".
As will be understood by those skilled in the art, an operation to transfer data from a pair of differential bit lines BL and /BL to a pair of differential input/output lines IO and /IO may be preceded by the operations of precharging and equalizing the potentials of the differential input/output lines IO and /IO at an intermediate potential between Vcc and GND (e.g., 1/2 Vcc). Then, after the transfer of data has taken place in response to a column select signal CSL, for example, an operation is performed to sense and amplify the data which has been transferred to the differential input/output lines IO and /IO. Unfortunately, in conventional integrated circuit memory devices, the timing of the operations to precharge and equalize the potentials of the differential input/output lines are not synchronized with the timing of the operation to transfer data from a pair of differential bit line BL and /BL to the pair of differential input/output lines IO and /IO. As a result, timing penalties may be incurred because excessive timing margins may be required to insure reliable equalization, transfer and sense operations when data in a memory device is being read. Such timing penalties can significantly limit the performance of such memory devices, particularly if the memory devices are expected to operate at extremely high frequencies.
Thus, notwithstanding the above-described integrated circuit memory devices, there continues to be a need for improved memory devices which are less susceptible to timing related penalties.